A method and a system of verifying access by a multi-core interconnect to an L2 cache (173) in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry (110) detects, in real time, interactions among a multi-core interconnects system (171), all single-core processors, an L2 cache (173) and a primary memory (172), and sends collected transmission information to an L2 cache expectation generator (120) and a check circuitry. The L2 cache expectation generator (120) obtains information from a global memory precise control circuitry (160) according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnecting access accuracy to the L2 cache (173) without delay.
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