INTEGRATED DEVICE COMPRISING AN ARRAY OF COMPUTE IN MEMORY (CIM) NAND OR NOR 8T-SRAM BITCELLS COMPRISING SHARED PRELOAD LINE AND SHARED ACTIVATION LINE

摘要

A memory circuit that includes an array of compute in memory (CIM) NAND or NOR 8T-SRAM memory bitcells comprising shared pre-load line and shared activation line. Each compute in memory (CIM) NAND or NOR 8T-SRAM memory bitcell includes a six-transistor (6T) SRAM circuit configuration, a first transistor coupled to the six-transistor (6T) SRAM circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.