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Processor core with support of an instruction set architecture for heterogeneous systems
Processor core with support of an instruction set architecture for heterogeneous systems
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机译:处理器核心支持异构系统的指令集架构
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摘要
Processor comprising: an instruction decoder; and an exception generation circuit for generating an exception in response to receipt of an unsupported command by the command decoder and notifying a command classification value of the unsupported command.
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