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Processor core supporting a heterogeneous system instruction set architecture
Processor core supporting a heterogeneous system instruction set architecture
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机译:处理器核心支持异构系统指令集架构
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摘要
Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.
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