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COUPLING WIDE MEMORY INTERFACE TO WIDE WRITE BACK PATHS
COUPLING WIDE MEMORY INTERFACE TO WIDE WRITE BACK PATHS
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机译:耦合宽的内存接口到宽回写路径
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摘要
Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.
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