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Improved Process for Programming Field Programmable Gate Arrays Using Partial Reconstruction

机译:使用部分重建的编程现场可编程门阵列的改进过程

摘要

Programming Field Programmable Gate Array (FPGA) Digital Electronic Integrated Circuits (ICs) and other ICs that Support Partial Reconfiguration - Certain FPGAs have reconfigurable partitions and configurable primitive variants in each of the reconfigurable partitions - Compile and store the primitive bitstreams for different primitive functions that may be implemented on a specific FPGA, before writing the configuration bitstreams to the FPGA; receiving input at the graphical user interface to connect graphical blocks representing the functional logic of an algorithm to be implemented on a particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of primitive functions that include specific primitive functions corresponding to graphics blocks; obtaining, from the digital storage, a subset of primitive bitstreams corresponding to the subset of primitive functions; It involves writing a subset of the primitive bitstreams to a particular FPGA using partial reconstruction operations.
机译:编程字段可编程门阵列(FPGA)数字电子集成电路(IC)和支持部分重新配置的其他ICS在每个可重新配置的分区中具有可重新配置的分区和可配置的原始变体 - 编译并存储不同原始函数的原始比特流可以在特定的FPGA上实现,然后将配置比特流写入FPGA;在图形用户界面处接收输入,以连接表示在特定FPGA上实现的算法的功能逻辑的图形块,与可重新配置逻辑有关的图形块;自动确定包含与图形块对应的特定原始函数的基本函数的子集;从数字存储获取与原始函数子集相对应的原始比特流的子集;它涉及使用部分重建操作将原始比特流的子集写入特定的FPGA。

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