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Improved field programmable gate array programming process with partial reconfiguration

机译:改进了现场可编程门阵列编程过程,具有部分重新配置

摘要

Programming Field Programmable Gate Array (FPGA) Specifics with primitive variations that are conformable on each of the Digital Electronic Integrated Circuits (ICs) or other ICs that support partial reconfiguration, reconfigurable partitions and reconfigurable partitions. FPGAs are capable of compiling and storing primitive bitstreams of different primitive functions that can be implemented in a particular FPGA and implementing algorithms in that particular FPGA, that is, before writing the configuration bitstream to the FPGA. Receiving input in a graphical user interface to connect a graphical block that represents the logic, the graphical block is associated with reconfigurable logic, receiving and specific primitive functions corresponding to the graphical block. Primitive bitstreams using automatic determination of the subset of primitive functions to contain, retrieving a subset of primitive bitstreams corresponding to the subset of primitive functions from digital storage, and partial reconfiguration operations. Includes writing a subset of to a particular FPGA. [Selection diagram] Fig. 2
机译:编程领域可编程门阵列(FPGA)细节具有在每个数字电子集成电路(IC)或支持部分重新配置,可重新配置的分区和可重新配置分区的每个数字电子集成电路(IC)或其他IC上的原始变型的细节。 FPGA能够编译和存储可以在特定FPGA中实现的不同基态函数的原始比特流,并在该特定FPGA中实现算法,即在将配置比特流写入FPGA之前。在图形用户界面中接收输入以连接表示逻辑的图形块,图形块与与图形块对应的可重新配置逻辑,接收和特定的基本函数相关联。原始比特流使用自动确定原始函数子集来包含,从数字存储和部分重新配置操作中检索对应于基元函数子集的原始比特流的子集。包括写入特定FPGA的子集。 [选择图]图2

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