首页> 外国专利> Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

机译:具有上间距漏极选择栅电极的三维存储器件和制造方法

摘要

An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.
机译:存储器堆叠结构阵列延伸穿过绝缘层的交替叠层和导电层。漏极选择级组件可以通过漏极选择级牺牲材料层形成漏极选择级开口,并且通过形成圆柱电极部分和第一栅极电介质Mayin的组合,每个第一排水选择 - 在漏极选择级开口的第二子集中直接在每个第二漏极选择电平开口的侧壁上形成第二栅极电介质的同时开口。通过用导电材料替换漏极选择级牺牲材料层来形成条带电极部分。填充漏极选择级别开口的第二子集的结构可以用作阵列的周边的虚设结构。伪结构是没有栅电极的,因此防止穿过其中的漏电流。

著录项

  • 公开/公告号US11037943B2

    专利类型

  • 公开/公告日2021-06-15

    原文格式PDF

  • 申请/专利权人 SANDISK TECHNOLOGIES LLC;

    申请/专利号US201916406283

  • 发明设计人 MUNEYUKI IMAI;JAMES KAI;

    申请日2019-05-08

  • 分类号H01L27/11556;H01L27/11582;G11C16/04;H01L29/06;H01L21/28;

  • 国家 US

  • 入库时间 2024-06-14 21:39:57

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