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Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
Machine Learning Based Methods and Apparatus for Integrated Circuit Design Delay Calculation and Verification
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机译:基于机器学习的集成电路设计延迟计算和验证的方法和装置
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摘要
A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.
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