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Clock generation circuitry for memory device to generate multi-phase clocks and output data clocks to sort and serialize output data
Clock generation circuitry for memory device to generate multi-phase clocks and output data clocks to sort and serialize output data
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机译:用于存储器设备的时钟生成电路生成多相时钟和输出数据时钟,以对输出数据进行排序和序列化
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摘要
A memory device may include a clock dividing circuit suitable for generating a plurality of internal clocks by dividing an external clock, a mode decision circuit suitable for determining an operation mode according to an input time point of a read command based on the internal clocks, a clock arranging circuit suitable for arranging the internal clocks in an order determined according to the operation mode, and outputting the arranged clocks as a plurality of data output clocks, and a data arranging circuit suitable for arranging read data according to the operation mode, and outputting the arranged data in response to the data output clocks.
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