Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus

摘要

A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.