PROBLEM TO BE SOLVED: To improve the efficiency of generating a netlist for a defect detection simulation. SOLUTION: A second layout to which node information of a first netlist D11 and a first netlist D11 whose connections are compared is added based on a netlist D10 of a semiconductor integrated circuit and a first layout pattern D20 of the semiconductor integrated circuit. A pattern D21 is generated, and the dust data D30 is moved in the X and Y directions of the second layout pattern D21 by a unit movement amount to generate a second netlist D12 that is a combination of a pair of nodes connected by the dust data D30. , When there is one second netlist D12 of the same node combination, one of them is added to the first netlist D11, and when there are multiple second netlists D12, a third netlist D11 for defect detection simulation is added. Generate a netlist D13. [Selection diagram] Fig. 2
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