PIPELINED INSTRUCTION READING METHOD AND APPARATUS BASED ON FPGA

摘要

A pipelined instruction reading method and apparatus based on an FPGA. The method may comprise: an on-chip processor on an FPGA chip determining a code program to be executed, wherein the on-chip processor is formed by the FPGA chip loading a circuit logic configuration file that has been deployed on an FPGA structure to which the FPGA chip belongs, and the code program corresponds to a smart contract called by a transaction and received by a blockchain node to which the FPGA structure belongs (102); and during a process in which the on-chip processor sequentially reads, according to a preset length, data contained in the code program, parsing the end bit of a non-fixed-length operation instruction contained in a data segment read each time, so that a data segment read next time is adjacent to the end bit (104).