CLOCK GENERATOR USING RESISTIVE COMPONENTS TO GENERATE SUB-GATE DELAYS AND/OR USING COMMON-MODE VOLTAGE BASED FREQUENCY-LOCKED LOOP CIRCUIT FOR FREQUENCY OFFSET REDUCTION

摘要

A clock generator (100) has a multi-phase controllable oscillator (104). The multi-phase controllable oscillator (104) includes oscillator core circuits (122[i]), and has phase nodes (P[i]) at which clock signals (CKOUT[i]) with different phases are generated, respectively. Each oscillator core circuit (122[i]) includes a resistive component (202) and an inverter (204). The resistive component (202) is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator (104), wherein clock signals (CKOUT[i]) generated at the first phase node and the second phase node have adjacent phases. The resistive components (202[i]) of the oscillator core circuits (122[i]) are cascaded in a ring configuration. The inverter (204) receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator (104), and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.