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binary system with at least one additive or subtraktiven halbaddierer

机译:具有至少一种加性或减除性哈尔巴第耶尔的二元体系

摘要

1,015,177. Digital computers. SPERRY RAND CORPORATION. May 1, 1963 [May 9, 1962], No. 17062/63. Heading G4A. An arrangement for indicating the " scale factor " of a binary number, i.e. the number of shifts required to bring the most significant digit of the number to a standard reference position, comprises an additive or subtractive half-adder and a " pyramid " for propagating carries or borrows, said pyramid being divided into groups, and is characterized by means responsive to signals generated by said groups for generating an indication of the scale factor of a binary number. The arrangement is applicable to the normalization of a number in a floating point computer. Arithmetic circuits.-The arrangement described is basically a fast adder circuit employing subtractive logic and comprises a first operand storage register X* and " difference " and " borrow " digit storage registers A and B representing the second operand. These three inputs are applied to a " half-subtractor " A* B* which is effectively a full adder employing subtractive logic but in which the carry input is externally applied from the B register. The output of the A* B* half-subtractor is applied to " difference " and " borrow " digit storage registers A* and B* whose outputs are applied to a " borrow pyramid " 17 effective to propagate the borrows. The output of the pyramid 17 is applied to a " main half-subtractor " 22 where the borrow digits and propagated borrows are half-subtracted from the difference digits to produce an output representing the sum of the input operands. The function of the borrow pyramid 17 is to propagate each borrow in the B* register to the left and end around if necessary until it finds a " 1 " in the A* register. To provide fast borrow propagation the 36-bit numbers in the A* and B* registers are regarded as arranged in six groups called Group A-Group F, each group having an associated " group borrow " circuit such as 16F, Fig. 3b. Each group borrow circuit produces a " group borrow " output on an associated lead 80 if there is a borrow originating within the group which cannot be absorbed within the group, a " group borrow enable " signal being produced by an inverter 98 if all the corresponding A* stages are " O " indicating that any borrow applied to the group cannot be absorbed within the group and should be applied to the next higher group. The " group borrow " and " group borrow enable " signals from the various groups are applied to " intrinsic group borrow " circuits such as 18F, Fig. 3b, which circuits produce an output if a borrow or borrows is to be satisfied within the corresponding group. These " intrinsic borrow " outputs are applied to corresponding group circuits such as 20F, Figs. 4a-4b, in a " final borrow propagation " circuit. Thus the Group F intrinsic borrow signal is applied on a lead IBF and is effective to enter an intrinsic borrow into each stage within Group F up to the lowest stage receiving a " 1 " from the A* register. The circuit 20F also handles the interstage borrows within a group which may be satisfied within the group and applies the borrows to the correct stages of the halfsubtractor 22, Fig. 1, which stages are divided into groups such as Group 22F, Figs. 4a, 4b, whose outputs ADD 00 &c. represented the required sum digits. Scale factor calculation.-The described circuit may be employed in a scale factor calculation since when the negative absolute value of a binary number is added to zero, the highest order initiating a group borrow is the highest order containing a significant digit. In operation, the negative absolute value of the binary number whose scale factor is required is entered into the X* register directly if negative and after complementing if positive, the registers A and B containing all zeros. The A* B* half-subtractor is then effective to place the complement of the contents of the X* register into both the A* and B* registers. A " group select " circuit 152 (Fig. 5, not shown), is then effective to determine the highest order group borrow circuit, Figs. 3a, 3b, which does not produce a group borrow signal and an output corresponding to this group is applied to a " scale factor generator " circuit 160 Fig. 6, and also to condition one of the group borrow circuits via a " group select " lead 82. The 36 outputs Aa-Ff from the individual stages of the group borrow circuits are applied to negative OR gates 192-202, Fig. 6, a signal being provided only on that output lead Aa-Ff corresponding to the highest order stage containing a borrow. Thus one only of a set of invertors 204-214 produces an output, #a-#f and this output is applied to the scale factor generator circuit 160, which consists of an array of gates, together with the group borrow select signal to provide a final output on leads 2SP0/SP-2SP5/SP representing in parallel form 36 minus the required scale factor value, which final output can be applied to a counter 162, Fig. 1, to control the left shift of the input number in a floating point normalization operation.
机译:1,015,177。数字计算机。斯普瑞兰德公司。 1963年5月1日[1962年5月9日],编号17062/63。标题G4A。用于指示二进制数的“比例因子”(即将数字的最高有效位数带到标准参考位置所需的移位数)的装置包括加法或减法半加法器和用于传播的“金字塔”携带或借用,所述金字塔被分成几组,并且其特征在于响应于由所述组产生的信号的装置,以产生二进制数的比例因子的指示。该布置适用于浮点计算机中数字的标准化。算术电路-所描述的装置基本上是采用减法逻辑的快速加法器电路,并且包括第一操作数存储寄存器X *和代表第二操作数的“差”和“借位”数字存储寄存器A和B。这三个输入被施加到一个“半减法器” A * B *,它实际上是采用减法逻辑的全加法器,但进位输入是从B寄存器外部施加的。 A * B *半减法器的输出被施加到“差”和“借位”数字存储寄存器A *和B *,它们的输出被应用于有效地传播借位的“借位金字塔” 17。金字塔17的输出应用于“主半减法器” 22,在该处,将借位数字和传播的借位从差数字中减去一半,以生成表示输入操作数之和的输出。借用金字塔17的功能是将B *寄存器中的每个借用向左传播,并在必要时结束,直到在A *寄存器中找到“ 1”为止。为了提供快速借位传播,将A *和B *寄存器中的36位数字安排为六个组,称为组A-组F,每个组具有关联的“组借位”电路,例如图3b中的16F。如果在组内存在不能在组内吸收的借用,则每个组借用电路在相关联的引线80上产生“组借用”输出,如果所有对应的借位都由逆变器98产生“组借用使能”信号。 A *阶段为“ O”,表示无法将任何借给该组的借贷吸收到该组内,而应将其应用于下一个更高的组。来自各个组的“组借用”和“组借用使能”信号被施加到“固有组借用”电路,例如图3b中的18F,如果要在相应的范围内满足借用或借用,则这些电路产生输出组。这些“固有借用”输出被施加到相应的组电路,例如20F,图1和2。在图4a-4b中,在“最终借用传播”电路中。因此,将F组固有借用信号施加到先导IBF上,并有效地将固有借入输入到F组中的每一级,直到从A *寄存器接收到“ 1”的最低级为止。电路20F还处理可能在该组内满足的组内的级间借用,并将该借用施加到图1的半减法器22的正确级,该级被分成诸如组22F,图2和图3的组。 4a,4b,其输出ADD 00&c。代表所需的总和数字。比例因子计算-所述电路可用于比例因子计算,因为当二进制数的负绝对值加零时,发起组借位的最高顺序是包含有效数字的最高顺序。在操作中,如果需要,则直接将其比例因子所需的二进制数的绝对值的负值输入X *寄存器;如果为正,则将其补码后,将寄存器A和B都包含全零。然后,A * B *半减法器可以有效地将X *寄存器的内容的补码放入A *和B *寄存器中。然后,“组选择”电路152(图5,未示出)有效地确定最高阶的组借用电路,图3和4。如图3a,3b所示,其不产生组借用信号,并且对应于该组的输出被施加到图6的“比例因子生成器”电路160,并且还经由“组选择”来调节组借用电路之一。引线82。来自组借用电路各个阶段的36个输出Aa-Ff被施加到图6的负或门192-202,仅在对应于最高阶的输出引线Aa-Ff上提供信号包含借款。因此,一组反相器204-214中只有一个产生输出#a-#f,并且该输出被施加到比例因子发生器电路160,该比例因子发生器电路160包括门阵列以及组借位选择信号以提供引线2 0 -2 5 上的最终输出以并行形式36减去所需的比例因子值,该最终输出可应用于图1的计数器162。,以控制浮点归一化操作中输入数字的左移。

著录项

  • 公开/公告号CH418008A

    专利类型

  • 公开/公告日1966-07-31

    原文格式PDF

  • 申请/专利权人 SPERRY RAND CORPORATION;

    申请/专利号CH19630005355

  • 发明设计人 FRANCIS MARETTEGEORGE;

    申请日1963-04-29

  • 分类号

  • 国家 CH

  • 入库时间 2022-08-23 15:08:01

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