Adaptive logic system with random selection, for conditioning, of two or more memory banks per output condition, and utilizing non-linear weighting of memory unit outputs

摘要

1,099,287. Adaptive translation circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 11, 1965 [June 29, 1964], No. 24716/65. Heading G4R. An adaptive translation circuit as described in Specification 1,050,627, in which digital input signals are applied to parallel-connected banks of adaptive memory units having conditioning circuits which cause them to assume predetermined states in response to predetermined input signals, the operation of the conditioning circuits being controlled in part by the storage states of the memory units, as represented by their outputs, is modified by the provision of selection means whereby at each conditioning operation a random selection is made of the bank of memory units to be conditioned. The conditioning signals are applied to each of the banks of memory units through corresponding groups of gates, only one of the groups of gates being opened by the selection means. The selection means consists of a continuously operating ring acting as a pulse distributer. The input to the ring is from a random noise source.