首页> 外国专利> method for manufacturing a, an isolated stuurelektrode veldeffecttransistor provided the verrijkingstype and veldeffecttransistor manufactured with this method.

method for manufacturing a, an isolated stuurelektrode veldeffecttransistor provided the verrijkingstype and veldeffecttransistor manufactured with this method.

机译:提供了一种隔离方法,该隔离型stuurelektrode veldeffect晶体管提供了用该方法制造的verrijkings型和veldeffect晶体管。

摘要

1,248,580. IGFETs. GENERAL ELECTRIC CO. 7 Oct., 1968 [13 Oct., 1967], No. 47482/68. Heading H1K. In making an IGFET the gate electrode is used to mask the semi-conductor during formation of the source and drain regions by diffusion. In one embodiment one or more pairs of complementary IGFETs are formed in an N-type silicon wafer 60 (Fig. 6) using common processing steps. First a genetic oxide layer 62 is formed on one face by heating in oxygen followed by annealing in helium. Molybdenum (or tungsten) 63 is then deposited overall by a glow discharge process and selectively removed from the sites of the sources and drains. A pure silica layer 75 is deposited overall and thinned by etching over the N channel IGFET sites prior to deposition of a boron-doped silica layer 76. The masking effect of the various oxide and molybdenum layers is such that in a subsequent heating boron diffuses inward to produce a continuous P-type base layer 82 at the site of each N channel device and spaced P-type source and drain inclusions 78, 79 where the oxide was not thinned. After removal of the boron doped oxide, phosphorus doped oxide 83 is applied over the N channel device sites by overall deposition followed by selective etching, and then diffused in. The molybdenum masks this diffusion to provide spaced N-type source and drain inclusions 86, 87 in each P-type base. Contacts and any desired interconnections are finally provided by suitably aperturing the insulating layers, depositing aluminium overall and then form etching. One or more N channel IGFETs only may be made on an N-type body by a simplified version of the above process. In this the boron doped film may be deposited directly: on the patterned molybdenum and the pure oxide either superposed on it before or after boron diffusion or dispensed with altogether. To form P channel devices on a P-type wafer, after forming the genetic oxide layer and molybdenum pattern phosphorus doped oxide is deposited and diffused in to form the sources and drains. A deposited layer of pure oxide may be provided between it and the pattern or on top of it. In a further alternative the pure oxide is deposited prior to patterning the molybdenum layer. In all the above processes the oxide layers are deposited by pyrolysis of ethyl orthosilicate alone or mixed with triethyl phosphate or borate where doping is required. Patterning of the various layers for forming masks, apertures, and contacts is effected by photoresist and etching steps using ferricyanide, a mixture of orthophosphoric, acetic and nitric acids; and hydrofluoric acid to remove molybdenum, aluminium and oxides respectively. Concentric and linear source and drain configurations are described. Where a number of identical devices are made on a common wafer it may subsequently be cut up and individual devices ohmically attached to headers using gold-indium alloy or donor-doped gold according to whether the wafer is P or N type.
机译:1,248,580。 IGFET。通用电气公司,1968年10月7日[1967年10月13日],第47482/68号。标题H1K。在制造IGFET中,在通过扩散形成源极区和漏极区的过程中,栅电极用于掩蔽半导体。在一个实施例中,使用共同的处理步骤在N型硅晶片60(图6)中形成一对或多对互补IGFET。首先,通过在氧气中加热然后在氦气中退火在一个面上形成遗传氧化物层62。然后通过辉光放电工艺将钼(或钨)63整体沉积,并有选择地从源极和漏极的位置去除。在沉积硼掺杂的二氧化硅层76之前,先沉积纯二氧化硅层75并通过在N沟道IGFET位置上进行蚀刻来使其变薄。各种氧化物和钼层的掩膜效果使得硼在随后的加热中向内扩散在每个N沟道器件的位置处形成连续的P型基极层82,并在氧化物没有变薄的地方隔开P型源极和漏极夹杂物78、79。除去掺杂硼的氧化物后,将掺杂磷的氧化物83进行整体沉积,然后进行选择性蚀刻,然后再扩散到N沟道器件的位置上,然后进行扩散。钼掩盖了这种扩散,以提供隔开的N型源极和漏极杂质86,每个P型基座中为87。最后,通过适当地对绝缘层进行穿孔,整体沉积铝,然后形成蚀刻,最终提供接触和任何所需的互连。通过上述过程的简化形式,一个或多个N沟道IGFET只能在N型主体上制成。在这种情况下,掺杂硼的膜可以直接沉积在图案化的钼和纯氧化物上,或者在硼扩散之前或之后叠加或完全省去。为了在P型晶片上形成P沟道器件,在形成遗传氧化物层和钼图案之后,沉积并扩散掺磷的氧化物以形成源极和漏极。可以在其与图案之间或在其顶部上提供纯氧化物的沉积层。在另一替代方案中,在图案化钼层之前沉积纯氧化物。在所有上述方法中,在需要掺杂的情况下,仅通过原硅酸乙酯的热解或与磷酸三乙酯或硼酸乙酯的热解来沉积氧化物层。通过光致抗蚀剂和使用氰化铁,正磷酸,乙酸和硝酸的混合物的蚀刻步骤来形成用于形成掩模,孔和接触的各种层的图案;和氢氟酸分别去除钼,铝和氧化物。描述了同心和线性源极和漏极配置。如果在一个普通晶片上制造了许多相同的器件,则可以将其切割,然后根据晶片是P型还是N型,使用金铟合金或掺杂施主的金将各个器件欧姆连接到集管上。

著录项

  • 公开/公告号NL6814114A

    专利类型

  • 公开/公告日1969-04-15

    原文格式PDF

  • 申请/专利权人

    申请/专利号NL19680014114

  • 发明设计人

    申请日1968-10-02

  • 分类号H01L11/14;H01L5/06;H01L7/46;H01L19/00;

  • 国家 NL

  • 入库时间 2022-08-23 12:47:44

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