Circuit arrangement for synchronously selection of data pulses of a sequence of equidistant clock pulses and not equidistant data pulses

摘要

1,126,160. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 26 Aug., 1967, No. 39369/67. Heading G4C. [Also in Division H3] A circuit for selecting regularly recurring pulses e.g. from a magnetic disc store comprises a gate and a ramp generator, the pulses providing one input to the gate and the other input being provided by the ramp when it exceeds a controlled value, the flyback of the ramp having a constant amplitude irrespective of ramp length and being initiated by the output of the gate. As applied to a magnetic disc store, binary data D (Fig. 2a) is represented by the presence and absence of a pulse between succesive clock pulses C. The data pulses cause the recorded clock pulses to be pushed apart, as shown dotted, but as the flyback is of constant amplitude the point at which the ramp (Fig. 2b) crosses the threshold T of the gating circuit is not affected. The input pulse train 2(a) alternatively may be derived (Figs. 3a-3g, not shown) from a signal (Fig. 3a) in which a change of binary data between its two values is represented by a change of phase of the signal. The signal is differentiated (3c) squared (3d) and produces pulses at the resulting leading and trailing edges (3c and f). These are combined to form the derived train (3g). Circuit details (Fig. 1).-The input pulses (2a) are applied at 13 to gate 14. The output pulses of the gate discharge capacitor 18 through diode 19 and the trailing edge transfers the charge to a Miller capacitor 21 to produce a determined magnitude of flyback. Capacitor 21 then discharges linearly to produce a ramp voltage (2b) at the input of transistor 32. The input of this transistor comprises a circuit which biases it to allow a predetermined portion of the end of the ramp to pass through transistors 32 and 37 to produce pulses 2(c) which are applied to the other input of gate 14 and thus to allow the next clock pulse to pass. The output from 32 is also applied to a gate 15 to block the clock pulses and allow the data to pass. An averaging circuit 26SP1/SP, 27 controls the rate of discharging of the Miller capacitor 21 so as to stabilize the amplitude of the sawtooth wave.