PARALLEL CODED SERIAL DIGIT ADDER WITH ADVANCED CARRY RECOGNITION

摘要

1,088,354. Adders. INTERNATIONAL COMPUTERS & TABULATORS Ltd. May 31, 1966 [June 1, 1965], No. 23214/65. Heading G4A. A serial adder generates the carry from one pair of digits in a shorter time than is required for adding them, and adds the carry to the next pair of digits, so that more than one pair of digits may be present in the adding circuitry at a time. In the serial-parallel adder of Fig. 1, each pair of multi-bit digits x, y is applied to a carry generator 3 and correspondingly ordered bits thereof are applied to respective bit adders 4, 7, 8, 9, each of which also receives any carry from the next lower order bit adder, except the lowest order bit adder 4 which receives any carry signal from generator 3. Delays 5, 6, 11- 17 are provided. In the carry generator 3, which is described, the carry output is obtained from a signal indicating whether a carry must be produced irrespective of the presence or absence of a carry from the next lower digit order, and one indicating whether a carry should be produced if such a lower order carry is present, the presence of such a lower order carry being indicated by feedback with effective delay from the output of the carry generator 3 itself. The invention may also be applied to a purely serial adder.