A DIGITAL MEASURING INSTRUMENT INCLUDING AN INTERGRATING ANALOGUE-TO-DIGITAL CONVERTER WITH A CLOCK OSCILLATOR AND APPARATUS FOR PHASE-LOCKING THE OPERATING FREQUENCY OF THE OSCILLATOR TO A REFERENCE FREQUENCY

摘要

1,245,578. Automatic phase control. SOLARTRON ELECTRONIC GROUP Ltd. 10 Sept., 1968 [11 Sept., 1967], No. 41428/67. Heading H3A. An analogue/digital converter in which a clock oscillator phase locked to a reference frequency comprises a discriminator responsive to a reference signal to sense periodic deviations of the oscillator frequency from a predetermined multiple of the reference frequency, and means responsive to such sensing to reduce the deviation in a stepwise manner. A mains frequency reference input is squared in unit 11 and divided by two in bi-stable 12 to produce on line 12a a 25 c/s. signal, the positive transitions of which set bi-stable 13 and open gate 14 to pass 1 Mc/s. pulses from oscillator 10 to counter 15. After a a count of 19,999 counter 15 produces an output which resets bi-stable 13. If the oscillator frequency is too high, bi-stable 13 is reset before the signal on line 12a makes its next negative transition, to produce a "1" on line 13b and a "0" on line 13a. When the negative transition occurs, this triggers bi-stable 17 to the state in which Q = 0 and Q = 1. During the 10 ms. preceding a positive transition on line 12a, gate 29 is opened to produce a "1" at its output. During the time that 12a and 13b are both "1", gate 32 passes pulses from oscillation 10 to counters 33, 30 and if more than two pulses are passed, 30 switches to "1". The outputs from units 29, 18, 30 are fed to AND gate 20 and coincident "1's" on all three inputs produce a positive signal on line 21. This is fed to diode pump 23 and integrator 24 to produce a signal to slow down the oscillator. If the oscillator frequency is too low, bistable 13 is not reset until after the signal on line 12a makes its next negative transition. When this transition occurs there is thus still a "1" on 13a and a "0" on 13b, and bi-stable 17 is triggered, to the state in which Q = 1 and Q = 0. In this case, during the time that a "1" exists at the outputs of 29, 30 the gate 19 is opened and a negative signal is produced on line 22. This is fed to diode pump 26 and integrator 24 to produce a signal to speed up the oscillator. Units 30 ... 33 provide a dead zone, no correction being applied unless 33, 30 count an error of at least plus or minus two cycles. Units 30 ... 33 may be omitted, and 19,20 replaced by two input gates.