DISTRIBUTED LOGIC MEMORY CELL FOR PARALLEL CELLULAR-LOGIC PROCESSOR

摘要

In a parallel cellular logic processor including a program control unit and a plurality of logic memory cells, all data inputs, except intercell inputs, for any cell are channeled through common input coupling logic to a one-bit intracell bus. The coupling logic is enabled or disabled in accordance with predetermined combinations of states of program control signals and of a plurality of control flip-flop circuits within the cell. Those flip-flop circuits receive data signal inputs from the bus. The same bus also provides data inputs for a data flip-flop circuit and for a data store within the cell. Data input to the bus is provided by way of the coupling logic from a program-selected one of the data flip-flop circuit, the store, an external source, or from program. Additional logic allows communication among cells by way of selective interconnection of their respective intracell buses as determined by further program control signals.