Flip-flop with lower power dissipation - consists field-effect transistors and invertor stages coupled together

摘要

Each invertor stage consists of a switching FET and a load FET, with the first switching FET drain connected to the gate of the second, and the first FET gate to the second FET drain. An AND gate consisting of two FEThs connected in series, is connected to the switching FET's drains. A further FET is between the gate of the AND gate's first FET, and the drain of corresponding switching FET's. The further FET's gates, and those of the AND gate second FET's are connected to the clock pulse inputs. Gates of the load FET's and their drains are connected to two supply voltage terminals respectively. Gates of both AND gate FET's and of load FET's are connected to an input for clock pulses, which serve as supply voltage source for the load FET's gates.