首页> 外国专利> Logic circuit based on complementary MOS transistors - has two gate stages each with three MOS transistors

Logic circuit based on complementary MOS transistors - has two gate stages each with three MOS transistors

机译:基于互补MOS晶体管的逻辑电路-具有两个栅极级,每个栅极级具有三个MOS晶体管

摘要

Each stage consist of a pair of MOS transistors in series with a logic block with at least one MOS transistor, inserted between two reference potentials. First stage output is connected to the gate of the second logic block transistor. Conduction type of the transistor which forms the second logic block is opposite to that of the first logic block transistor. The output stage of each transistor is earthed through an earthed condenser. The control electrodes of the driver transistors in the first and second gate circuit elements are connected respectively with the first and second sources of the pulses, the second source being the inverse of the first.
机译:每级包括一对MOS晶体管,该MOS晶体管与一个逻辑模块串联,该逻辑模块具有至少一个MOS晶体管,并插入两个参考电位之间。第一级输出连接到第二逻辑块晶体管的栅极。形成第二逻辑块的晶体管的导电类型与第一逻辑块晶体管的导电类型相反。每个晶体管的输出级通过接地的电容器接地。第一和第二栅极电路元件中的驱动器晶体管的控制电极分别与脉冲的第一和第二源连接,第二源与第一的反相。

著录项

  • 公开/公告号DE2450882A1

    专利类型

  • 公开/公告日1975-10-23

    原文格式PDF

  • 申请/专利权人 HITACHILTD.;

    申请/专利号DE19742450882

  • 发明设计人 FUKUDAHIDEKI;

    申请日1974-10-25

  • 分类号H03K19/08;G11C11/40;

  • 国家 DE

  • 入库时间 2022-08-23 03:52:19

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