Frequency adder circuit for square wave pulses - uses positive logic NAND-gates, inverters and flip-flops

摘要

The frequency adder circuit for square wave pulses of different frequencies consists of a series of inverters and NAND-gates. The pulse train with the highest frequency is connected to the first input terminal of the circuit, which is the input to an inverter (3) and one of the inputs of a three-input NAND-gate (8). The outputs of the first and fourth inverters form the inputs of another NAND-gate (7), whose output is one of the inputs of a similar gate forming the final output element (9). The lower of the two pulse frequencies is connected to the clock input of an edge-triggered flip-flop (10). The second half of which has its Q output connected to the final NAND-gate (9).