Integrated semiconductor circuit with MIS logic circuit - responds to at least one input signal and delivers output signal using complementary inverting stage

摘要

The output signal level is determined by the presence or absence of charges in a load capacitance. The output wire is crossed by a second signal wire. A complementary inverting stage is connected by one end to a voltage source potential and it is connected by the other end a reference potential. It is inserted into the output wire (11) between the MIS logic circuit and the crossing point between the output wire and the other signal wire.