CLOCK FREQUENCY STABILIZATION CIRCUIT IN A-C CONVERTER WITH DOUBLE INTEGRATIONPREOBRAZOVATELE S DVOJJNYM INTEGRIROVANIEM

• 1. 一种双斜分数阶积分式模数转换器 [P] . 中国专利： CN108693400B . 2021.01.05
• 2. 一种双斜分数阶积分式模数转换器 [P] . 中国专利： CN108693400A . 2018-10-23
• 3. CLOCK FREQUENCY STABILIZATION CIRCUIT IN A-C CONVERTER WITH DOUBLE INTEGRATIONPREOBRAZOVATELE S DVOJJNYM INTEGRIROVANIEM [P] . PL120251B1 . 1982-02-27

  机译： 双积分A-C转换器的时钟频率稳定电路压电式转子DVOJJNYM积分式

• 4. SYSTEM OF CURRENT SOURCES IN A/C CONVERTER WITH DOUBLE INTEGRATIONELE S DVOJJNYM INTEGRIROVANIEM [P] . PL121992B1 . 1982-06-30

  机译： 双积分的A / C转换器电流源系统DVOJJNYM INTEGRIROVANIEM

• 5. SYSTEM OF CURRENT SOURCES IN A/C CONVERTER WITH DOUBLE INTEGRATIONELE S DVOJJNYM INTEGRIROVANIEM [P] . PL206628A1 . 1980-02-11

  机译： 双积分的A / C转换器电流源系统DVOJJNYM INTEGRIROVANIEM

• 1. Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power [C] . Reuben John Computing, Electronics and Electrical Technologies (ICCEET), 2012 International Conference on . 2012
• 2. CMOS auto-ranging phase -locked loop integrated circuits for frequency synthesizers and clock recovery circuits [D] . Chang, Yi-Cheng 2000
• 3. Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip [O] . Danny Dolev, Matthias Függer, Markus Posch, -1
• 4. 24.9 Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits [O] . Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, 2015
• 5. Mixed Frequency-Time Approach for Finding the Steady-State Solution of Clocked Analog Circuits [R] . Kundert, K., White, J., Sangiovanni-Vincentelli, A. 1988

• 1. 双积分模数转换器芯片中部分电路的设计与实现 [A] . 杨荣彬 . 2008