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Local oscillator circuit having two phase locked loops having respective frequency dividers with a common division ratio

机译:具有两个锁相环的本地振荡器电路,两个锁相环具有各自的分频器,并具有共同的分频比

摘要

A first phase locked loop produces a local oscillator signal. The output of a second phase locked loop is connected to the input of the first phase locked loop. A first variable frequency divider is connected in the first phase locked loop. A second variable frequency divider having the same frequency division ratio as the first frequency divider is connected between a variable frequency oscillator and the input of the second phase locked loop. An adder adds a base frequency of preferably 1 MHz to the output frequency of the second frequency divider. With the frequency of the variable frequency oscillator set at a center frequency, the frequency of the local oscillator signal is equal to the frequency division ratio of the frequency dividers multiplied by 1 MHz. Any variation in the frequency of the variable frequency oscillator from the center frequency is algebraically added to the local oscillator frequency, regardless of the frequency division ratio, as an offset frequency. The frequency range of the variable frequency oscillator is low compared to the frequency range of the local oscillator signal, thereby enabling low frequency drift. A gate disables the first phase locked loop when the second phase locked loop is not in lock.
机译:第一锁相环产生本地振荡器信号。第二锁相环的输出连接到第一锁相环的输入。第一可变分频器连接在第一锁相环中。具有与第一分频器相同的分频比的第二可变分频器连接在可变频率振荡器和第二锁相环的输入之间。加法器将优选为1MHz的基本频率加到第二分频器的输出频率上。在将可变频率振荡器的频率设置为中心频率的情况下,本地振荡器信号的频率等于分频器的分频比乘以1 MHz。可变频率振荡器的频率相对于中心频率的任何变化都被代数加到本地振荡器频率上,而与分频比无关,作为偏移频率。与本地振荡器信号的频率范围相比,可变频率振荡器的频率范围低,从而实现了低频漂移。当第二锁相环未锁定时,门将禁用第一锁相环。

著录项

  • 公开/公告号US4225829A

    专利类型

  • 公开/公告日1980-09-30

    原文格式PDF

  • 申请/专利权人 ALPS ELECTRIC CO. LTD.;

    申请/专利号US19780963348

  • 发明设计人 TADASHI KUMAGAI;

    申请日1978-11-24

  • 分类号H03B3/04;

  • 国家 US

  • 入库时间 2022-08-22 17:01:02

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