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Circuit arrangement for clock pulse recovery at the receiving end of digital clock-controlled data transmission systems
Circuit arrangement for clock pulse recovery at the receiving end of digital clock-controlled data transmission systems
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机译:在数字时钟控制的数据传输系统的接收端用于时钟脉冲恢复的电路装置
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摘要
A circuit arrangement for clock pulse recovery on the receiving side of a digital clock-controlled data system is particularly characterized in that in the receiver a branch circuit is connected to the input side in parallel with a digital converter for converting the digital data signal, the branch circuit comprising an EXCLUSIVE or gate having two inputs and a delay element in the feed to one input of a digital counter which is connected to the output of the EXCLUSIVE OR gate and actuated by a quartz-stabilized oscillator having a frequency of multiple of the desired timing frequency and whose output is connected to the digital converter.
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