首页> 外国专利> Conductor pattern for semiconductor device on insulating substrate - where multilayer pattern includes palladium covered by palladium oxide and then gold

Conductor pattern for semiconductor device on insulating substrate - where multilayer pattern includes palladium covered by palladium oxide and then gold

机译:绝缘基板上半导体器件的导体图案-多层图案包括先被氧化钯覆盖的钯,再被金覆盖

摘要

The substrate is made esp. of alumina or glass, which is covered with a multilayer conductor pattern. The pattern consists of a first layer (a) of CrNi, which is covered by Ti (b) and then Pd(c). On top of the Pd(c) is a layer (d) of PdO, and then a layer (e) of gold. The gold layer (e) is pref. more than 1000 nm thick, esp. 2000 nm thick with a Pd layer (c) of ca. 400 nm. Alternatively, the Au (e) may be less than 500 nm thick, esp. 50-120 nm thick. The CrNi(a) pref. has a resistance of e.g. 100 ohms/square, whereas the Ti(b) is pref. 50 nm thick. Used esp. for highly integrated coding/decoding semiconductor circuits in a long-distance digital telephone exchange. The conductor patterns are used to make joints by soldering, or bonding. A layer of PdO can form on the Pd(c) before the Au is deposited, but is not detrimental to the pattern; and in many cases a very thin layer (e) of gold may be used so cost is reduced.
机译:基材特别是制成。覆盖多层导体图案的氧化铝或玻璃。该图案由CrNi的第一层(a)组成,该层被Ti(b)和Pd(c)覆盖。在Pd(c)的顶部是PdO层(d),然后是金(e)层。金层(e)是优选的。大于1000 nm的厚度,特别是2000纳米厚的Pd层(c)约为400纳米备选地,Au(e)可以小于500nm厚,尤其是。 50-120 nm厚。 CrNi(a)优选。具有例如100欧姆/平方,而Ti(b)为首选。 50纳米厚。二手的用于长距离数字电话交换机中的高度集成的编码/解码半导体电路。导体图案用于通过焊接或粘接来形成接头。在沉积Au之前,可以在Pd(c)上形成一层PdO,但这对图案没有不利影响。在许多情况下,可以使用非常薄的金(e)层,因此可以降低成本。

著录项

  • 公开/公告号DE3029382A1

    专利类型

  • 公开/公告日1982-03-04

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号DE19803029382

  • 发明设计人 SMOLAJAN;

    申请日1980-08-01

  • 分类号H05K1/09;

  • 国家 DE

  • 入库时间 2022-08-22 12:42:53

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