Four gate frequency divider acting as up=down counter - has delayed and non delayed collector outputs and two additional input gates

摘要

This frequency divider comprises two cascaded flip-flops based on integrated injection logic technique. It is developed into an up/down counter which may be preloaded any time. This is achieved by including a delay element in one of the collector output lines. Set and reset facilities are obtained by adding two further gates to the input circuit. One gate (3) of the output flip-flop has a delay element (D) in one of its three collector output lines (321). The two collectors of a fifth gate (5), forming the reset input (R) are connected to the clock input(T) of the first flip-flop (1,2) and the sixth gate (6) forming the set- input has three collector outputs one of which (61) includes a delay element (D) and is connected to the second flip-flop output gate (3).