Digital phase difference measurement circuit has oscillator circuit with gates, delay device that feeds delayed clock signal back to second gate, counter circuit connected to oscillator circuit output to produce phase difference signal

摘要

The circuit arrangement (10) has an oscillator circuit (14) with a first equivalence or antivalence gate (15) receiving an actual signal and a reference signal, a second NAND gate (16) receiving the output of the first gate and that produces a clock signal, a delay device (17) connected to the output of the second gate and that feeds the delayed clock signal to a second input of the second gate and a counter circuit connected to the output of the oscillator circuit and producing a phase difference signal. An independent claim is also included for a phase-locked loop.