Management unit coupling memory devices to data bus - using clock input for each decoder linked memory input

摘要

A connection management unit for coupling a memory device to a data bus has a clock frequency channel and a control channel. It enables an optional number of memory devices to be connected to a serial interface port of a microprocessor. The unit has a simple circuit design and can be incorporated on the same chip as a memory device. The serial data bus (13,14) is connected to the memory device (10) via an address decoder (20) so that each memory input connected to the decoder has an associated clock input which controls it. The clock inputs are controlled sequentially by a clocking frequency divider (18) in a defined sequence. The data bus is connected to the memory device via a bidirectional gate (19) controlled via the control channel (12).