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TRIPLE PROCESS INPUT AND OUTPUT DEVICE

机译:三重过程输入和输出设备

摘要

PURPOSE:To improve the reliability, by providing a signal receiving/processing part to each triple device to check the soundness of the signal which is received from a central computer and setting the output to be fed to a majority circuit at an extreme value when the signal is faulty. CONSTITUTION:A central computer 1 is connected to transmission/reception processors 3a-3c via a bus 2 and couplers 22a-22c. The relay contacts 5a- 5c are connected to a processor 7 via an analog majority logic 6. The signal 11 detected through the processor 7 is fed to the processors 3a-3c respectively. These signals are processed by a command of an arithmetic processor 31 and then fed to the computer 1 via a transmission control unit 32. The signal sent from the computer 1 is fed to a memory 33 under the control of the processor 31 via the unit 32 and at the same time receives a D/A conversion 35 to be fed to the logic 6 through the contact 5a. The signal of the converter 35 receives an A/D conversion 34 again and is compared with the contents of the memory 33. If a discordance is detected through a self-diagnosing unit 37, a relay 4a is driven by a fault processing unit 38 to break the contact 5a.
机译:目的:为提高可靠性,通过为每个三重设备提供一个信号接收/处理部分,以检查从中央计算机接收到的信号的健全性,并在输出信号时将要馈送到多数电路的输出设置为极值。信号有故障。组成:中央计算机1通过总线2和耦合器22a-22c连接到发送/接收处理器3a-3c。继电器触点5a-5c经由模拟多数逻辑6连接到处理器7。通过处理器7检测到的信号11分别馈送到处理器3a-3c。这些信号由算术处理器31的命令处理,然后经由传输控制单元32馈送到计算机1。从计算机1发送的信号在处理器31的控制下经由单元32馈送到存储器33。并同时接收D / A转换35,以通过触点5a馈送到逻辑6。转换器35的信号再次接收A / D转换34,并且与存储器33的内容进行比较。如果通过自诊断单元37检测到不一致,则由故障处理单元38驱动继电器4a,以将其输出到存储器35。断开触点5a。

著录项

  • 公开/公告号JPS5890201A

    专利类型

  • 公开/公告日1983-05-28

    原文格式PDF

  • 申请/专利权人 HITACHI SEISAKUSHO KK;

    申请/专利号JP19810186852

  • 发明设计人 NOGUCHI SEKIKEN;ISHII KAZUHIKO;

    申请日1981-11-24

  • 分类号G05B9/03;

  • 国家 JP

  • 入库时间 2022-08-22 11:30:10

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