Frame structure suitable for multiplexing signals of very different bit rate

摘要

The invention creates a frame structure suitable for multiplexing signals of very different bit rate, with an additional information item for positive clock adaptation, used for alignment and for signalling clock deviations. To multiplex a fast signal with a bit sequence of 34368 kbit/s with a slow signal with a bit sequence of 1024 kbit/s to form a multiplex bit stream of 351520 kbit/s, 33 bits of the fast signal and 1 bit each of the slow signal are in each case combined to form a time slot which is repeated 128 times within the frame. The frame begins with 13 additional bits, 7 bits of which are used for signalling clock adaptations for the fast signal, 5 bits of which are used for signalling clock adaptations for the slow signal and 1 bit of which is used for signalling alarm messages. Of the 13 additional bits, the 12 bits used for signalling clock adaptation are used at the same time as frame alignment word. In time slots 32 and 96, bit 34 is in each case used for transmitting service information items. At a clock rate of 341368 kbit/s and a permissible clock deviation of +/-20.10-6 for the fast bit sequence, the relative clock deviation of the multiplex signal is allowed to be +/-82.10-6. It is preferably reduced to +/-20.10-6 in accordance with CCITT Recommendation G.751. IMAGE