首页> 外国专利> Process for inspecting objects showing patterns with dimensional tolerances and reject criteria varying with the locations of said patterns and apparatus and circuits for carrying out said process

Process for inspecting objects showing patterns with dimensional tolerances and reject criteria varying with the locations of said patterns and apparatus and circuits for carrying out said process

机译:用于检查显示具有尺寸公差的图案和拒绝标准的对象的方法,所述拒绝标准随所述图案的位置以及用于执行所述方法的设备和电路而变化

摘要

First of all, this invention relates to a process based on the comparison of the image of a reference object I.sub.ref with the image of an object to be inspected I.sub.exa. Images I.sub.ref and I.sub.exa are picked-up, sampled, discretized and thresheld to produce electronic or binary images I.sub.REF and I.sub.EXA, respectively. These images are cleaned, then centered, I.sub.REF is adjusted to the minimum dimensional tolerances and becomes (I.sub.REF).sub.min. For each image point (pixel), the adjustment is performed by using a structuring element of variable size, the size of which is controlled by a bus from the data contained in a memory unit which take the location of the pixel on the reference object, into account. (I.sub.REF).sub.min is compared to I.sub.EXA which ensures the following function: ##EQU1## The resulting image is the image of the "lack" type defects (which does not appear in I.sub.exa with respect to I.sub.ref). Each defect is studied in a defect analysis unit which computes the dimensions of the defect and compares these dimensions with the maximum allowed size of the defect in this location. For this purpose, this circuit uses the reject criteria for this location, which are contained in a memory unit. The processing operations (adjustment and analysis) and the production of the corresponding data contained in the memory, are synchronized by count and delay circuits. The binary result (accepted/rejected) is available on a line. The defects of the "spreading" type are processed in the same way. The logic level of the line which is connected to a computer, determines the final decision (accepted/rejected). This invention also relates to an apparatus and circuits for carrying out the described process. This invention can be more particularly used in manufacturing semiconductors (masks, modules, chips, . . . ).
机译:首先,本发明涉及一种基于比较参考物体Iref的图像与被检查物体Iexa的图像的过程。图像Iref和Iexa被拾取,采样,离散化和阈值化以分别产生电子图像或二进制图像Iref和IEXA。清洁这些图像,然后居中,将IREF调整到最小尺寸公差,并变为(IREF)min。对于每个图像点(像素),通过使用大小可变的结构元素来执行调整,该大小可变的结构元素的大小由总线根据存储在存储单元中的数据控制,该数据获取像素在参考对象上的位置,考虑在内。 (I.sub.REF).sub.min与I.sub.EXA进行比较,以确保以下功能:## EQU1 ##生成的图像是“缺失”类型缺陷的图像(在I中未出现)关于I.sub.ref)。在缺陷分析单元中研究每个缺陷,缺陷分析单元计算缺陷的尺寸并将这些尺寸与该位置的最大允许尺寸相比较。为此,该电路使用此存储单元中包含的拒绝标准。处理操作(调整和分析)以及包含在存储器中的相应数据的生成由计数和延迟电路同步。二进制结果(接受/拒绝)在线上可用。 “扩展”类型的缺陷以相同的方式处理。连接到计算机的线路的逻辑电平确定最终决定(接受/拒绝)。本发明还涉及用于执行所述过程的设备和电路。本发明可以更特别地用于制造半导体(掩模,模块,芯片等)。

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