CIRCUIT FOR COMPENSATING VARIATION OF MARK RATE

摘要

PURPOSE:To compensate the variation of a mark rate by coupling a front stage FET and a post stage FET in terms of AC and amplifying a source potential of the front stage FET so as to control the gate of the post stage FET thereby making the amplitude of an input signal having the mark rate dependancy constant. CONSTITUTION:A mutual conductance gm of the FETs Q1, Q2 is increased when a gate voltage is increased and a base potential of a transistor (TR) Q3 is increased and a collector potential is lowered when the source potential of the front stage FETQ1 is increased. As a result, the conductance gm of the post stage FETQ2 is decreased, and when a signal level of the terminal IN is lowered conversely, the collector potential of the TRQ3 is increased, the conductance gm of the FETQ2 is increased, resulting in that the value of the conductance gm is controlled so that the output level of the FETQ2 is made constant. Thus, the fluctuation of a DC level due to the variation of the mark rate attended with AC coupling is compensated.