Virtual addressing system using page field comparisons to selectively validate cache buffer data on read main memory data

摘要

A buffer memory system comprises a buffer memory and a fetch directory. Both are accessible by a concatenation of at least the least significant bit of logical or physical page field of a logical or a physical address signal and a selected number of bits lower than that least significant bit. Physical page fields stored in the fetch directory are used to control an access to a data block stored in the buffer memory even at a plurality of addresses accessible by logical and physical address signals for one and the same instruction for accessing the memory. The system may or may not comprise an inverse translation table for translating a physical address signal for accessing a main memory into the concatenation to be used in accessing the buffer memory and the control table.