Multiprocessor system with cache memory - has common bus connected to addressable main memory for transferring address and data

摘要

The multiprocessor system has a number of central processor units sharing the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, and cache memory control determines if the addressed data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache memory, the cache memory control gains acces to the bus by a priority circuit data reads out the data from memory, storing the data in the cache memory at the same time that it transfers the data to the processor.