LSSD-TESTABLE D-TYPE EDGE-TRIGGER-OPERABLE LATCH WITH OVERRIDING SET/RESET ASYNCHRONOUS CONTROL

摘要

ABSTRACT OF THE DISCLOSUREA LSSD testable latch circuit apparatus isdisclosed which has systems operational andLSSD testing operational modes. The apparatusis arranged with first and second groups offlip-flops, each group having three flip-flops.Control means allows for selective operation ofthe first group of flop-flops as a D-type edgetriggered latch during the systems operationalmode and of the first and and second groups asa three-stage shift register during the LSSDtesting operational mode. The control meansalso allows the D-type edge-triggered latch tohave override asynchronously set and/or resetcontrol.