LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control

摘要

A LSSD testable latch circuit apparatus is disclosed which has systems operational and LSSD testing operational modes. The apparatus is arranged with first and second groups of flip-flops, each group having three flip- flops. Control means allows for selective operation of the first group of flop-flops as a D-type edge triggered latch during the systems operational mode and of the first and second groups as a three- stage shift register during the LSSD testing operational mode. The control means also allows the D-type edge-triggered latch to have override asynchronously set and/or reset control.