A CELLULAR FLOATING-POINT SERIAL-PIPELINED MULTIPLIER

摘要

A cellular floating-point serial pipelined multiplier arranged to accept two synchronous digit serial data streams in floating-point format and output one identically formatted stream which is the floating-point product of the synchronous input members, comprising a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand connected to a pipelined addition circuit (3) which outputs the product through a delay cell (6), a MODE control signal propagation and generation circuit (4) connected to the pipelined addition circuit (3) and to the digit re-ordering/delay circuit (2), and a cell differentiation circuit (5) connected to control the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2) and the X operand delay circuit (1).