Clock divider circuit incorporating a J-K flip-flop as the count logic decoding means in the feedback loop

摘要

A circuit approach is illustrated for simplifying a count divider circuit by applying selected outputs of the counter to a J-K flip- flop as input to the J-K terminals whereby a comparatively high speed response is returned for presetting the counter as compared to the prior art approach which either required much more circuitry or intolerable time delays.