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Minimal logic synchronous up/down counter implementations for CMOS
Minimal logic synchronous up/down counter implementations for CMOS
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机译:CMOS的最小逻辑同步向上/向下计数器实现
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摘要
A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.
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