PURPOSE:To realize the high speed transfer of a Kanji (Chinese characters) pattern and to reduce the processing load of CPU, by providing a DMA circuit for performing the block transfer of the Kanji pattern to a line buffer and an address converting circuit. CONSTITUTION:A pattern converting circuit 4 inputting a Kanji pattern 42 supplies a pattern transfer demand signal 43 to a DMA circuit 10 which is turn outputs a bus use demand signal 11 to CPU 2 and inputs the bus use permitting signal 21 of CPU 12. Further, the DMA circuit 10 supplies an internal address signal 12 and a control output signal 13 to an address converting circuit 20 which in turn connects a pattern converting circuit 4 and a main memory part 5 through an address bus 30. A data bus 40 supplies data to the address converting circuit 20. By this DMA circuit 10 and the address converting circuit 20, block transfer is performed at a high speed regardless of the discontinuous address at a forwarding address.
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