PURPOSE:To attain data transfer corresponding to the internal timing of a scanner to a high speed circuit as well by executing the cycle steal of a control storage in the succeeding scanning time. CONSTITUTION:When a data transfer instruction for instructing the cycle steal of control information read out from a control storage (PLA)4 is ON in the initial scanning time for the transmission/reception of the final bit to/from an external interface, the instruction is stacked on the CSREQ bit of a cycle steal control area in an interface control word (ICW)21 and the scanning processing is executed to end the processing once. The ICW21 is accessed in the succeeding scanning, and when a cycle steal request (SCREQ) is recognized, the cycle steal is executed and data stored in a channel buffer of the ICW21 are taken out and stored in the control storate (CS)3.
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