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Phase-locked loop coefficient generator for a filter arrangement having a non-rational ratio between input and output sampling frequencies
Phase-locked loop coefficient generator for a filter arrangement having a non-rational ratio between input and output sampling frequencies
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机译:用于滤波器装置的锁相环系数发生器,该滤波器装置在输入和输出采样频率之间具有非合理比率
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摘要
In a sample rate converter having a non-rational conversion factor the input samples coincide with low-rate clock pulses and the output samples coincide with high-rate clock pulses, or inversely. It comprises a filter coefficient generator 3 which, based on the distance (deviation) between a low-rate clock pulse and the immediately preceding or immediately subsequent high-rate clock pulse, continuously supplies a series of filter coefficients. To determine the deviation a phase-locked loop (30) is provided, with a phase detector (301) receiving the low-rate clock pulses as well as synthetic low-rate clock pulses and supplying a discrete-time phase difference signal u(.) which is applied to a processor circuit (302). This circuit supplies the desired deviation d(.) and a reference number N which is applied to a counter circuit (304). This circuit also receives the high-rate clock pulses and each time after receiving the number of clock pulses corresponding to the reference number it supplies a synthetic low-rate clock pulse. In the processor circuit 302 a filtering operation (3021) is first performed on the discrete-time phase difference signal u(.) so that control signal samples H(.) are obtained. An auxiliary sample s(.) is subtracted from such a control signal sample and the difference is divided by a weighting factor incr. of the number P thus obtained those bits whose significance is less than 2° represent the deviation d(.), while the other bits represent the reference number N. By subsequently multiplying the deviation d(.) by the weighting factor incr, a new auxiliary sample s(. + 1) is obtained.
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