A FRACTIONED CONVERSION CONVERSION CONVERTER HAVING AN ISOLATION CIRCUIT BETWEEN A SUBTRACTION NODE AND A LOW WEIGHT BIT ENCODER

摘要

THE INVENTION CONCERNS ANALOG-TO-DIGITAL CONVERTER TECHNOLOGY. A 12-BIT CONVERSION ANALOGUE-DIGITAL CONVERTER INCLUDES, IN PARTICULAR, A SAMPLE-BLOCKING CIRCUIT 3, AN INSTANTANEOUS ENCODER OF HIGH-BIT BITS. 17, A PRECISION DIGITAL-TO-ANALOG CONVERTER 36 THAT ATTACKS A SUMMING NODE 38, A LOW WEIGHT BIT ANALOG TO DIGITAL CONVERTER 48 AND A DIGITAL ERROR CORRECTION CIRCUIT 61 THAT PROVIDES THE OUTPUT SIGNAL. THE SAMPLE ANALOGUE INPUT SIGNAL IS TRANSMITTED DIRECTLY TO THE SUM TEMPERATURE WHICH IS SUBTRACTED FROM THE DIGITAL-TO-ANALOG CONVERTER OUTPUT SIGNAL. TWO FIELD EFFECT TRANSISTORS 39, 40 ARE INTERCALE BETWEEN THE SUMMING NODE AND A DIFFERENCE AMPLIFIER 43 TO ESTABLISH A SELECTIVE CONNECTION BETWEEN THESE ELEMENTS TO AVOID AN OVERLOAD OF THE INPUT OF THE AMPLIFIER BEFORE THE STABILIZATION OF THE SIGNAL OF OUTLET OF THE SAMPLE-BLOCKER CIRCUIT. / P P APPLICATION TO HIGH-PRECISION FAST ANALOG-TO-DIGITAL CONVERTERS. / P