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Dielectric insulation type semiconductor integrated circuit having low withstand voltage devices and high withstand voltage devices

机译:具有低耐压器件和高耐压器件的介电绝缘型半导体集成电路

摘要

At the bottom of an island region in which a low withstand voltage transistor is formed, is provided a high concentration region of the same conductivity type as the island region having a larger thickness than a high concentration region provided at the bottom of an island region in which a high withstand voltage transistor is formed, and the bottom surfaces and side surfaces of the respective island regions are fixedly secured to a polycrystalline semiconductor layer via insulator films.
机译:在其中形成有低耐压晶体管的岛状区域的底部,提供了与该岛状区域具有相同导电类型的高浓度区域,该高浓度区域具有比设置在岛状区域的底部中的高浓度区域更大的厚度。形成高耐压晶体管,并通过绝缘膜将各岛区域的底面和侧面固定在多晶半导体层上。

著录项

  • 公开/公告号US4692784A

    专利类型

  • 公开/公告日1987-09-08

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19840599158

  • 发明设计人 TATSUO NEGORO;

    申请日1984-04-11

  • 分类号H01L29/06;H01L27/12;H01L29/04;

  • 国家 US

  • 入库时间 2022-08-22 07:08:50

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