Chrominance signal phase locked loop system for use in a digital television receiver having a line-locked clock signal

摘要

A digital television receiver which uses a line-locked clock signal employs chrominance signal demodulation circuitry which produces a digital oscillatory signal that is locked in phase to the color reference burst signal component of the incoming video signals. An analog voltage controlled oscillator generates an oscillatory signal having a frequency of approximately twice the color subcarrier frequency. This signal is combined with the composite video signals and the combined signal is digitized by an analog to digital converter. The digitized oscillatory signal is separated from the combined digital signal and is used to synchronize a digital phase locked loop. The digital phase locked loop generates two quadrature phase related signals having frequencies that are one-half the frequency of the analog oscillatory signal. These two signals are used to synchronously demodulate the chrominance signal components of the incoming video signals to obtain two quadrature phase related color difference signals. The control signal for the voltage controlled oscillator is generated by subtracting the burst phase of the demodulated color difference signals from a reference phase and integrating the difference.