Receiver decoding control circuit for TV transmission system - uses phase locked loop and pseudo-random digital sequence generator to provide delay to line sync. signal

摘要

Coded signals are amplified (10) and applied to three parallel channels (20) containing weighted delays (O,R,2R) terminated by switches (21,22,23). The amplifier output passes through a separator (50) to extract line (L) and frame (T) sync. signals. A phase locked loop (60) provides a signal which defines a time window for each line sync. signal. This window signal is applied to a logic control circuit (70) to operate the three channel switches (21,22,23) when a signal is issued by a pseudorandom digital sequence generator (80). This generator operates if a valid image signal is received. A frame suppression recognition signal generator (90) provides an operational signal when a line sync. signal is received. This avoids disturbance to the image during this period. A coding recognition signal generator (100) provides a validation signal on reception of coded transmission to operate the switches.